Digital logic consists of combinational logic functions and sequential logic functions. In combinational logic functions, the digital output(s) is determined by the present data state of its input data signals. Any change in an input data state of a combinational logic function results in an immediate change in the function's output data state. Examples of combinational logic functions are AND gates (a TRUE state on ALL inputs results in a TRUE state on the output), OR gates (a TRUE state on ANY input results in a TRUE state on the output), and multiplexers (the output state is derived from one of a set of inputs that is selected from another set of inputs). Sequential logic functions differ in that an output data (Q) state can maintain a data state that is dependent on the input data states that were applied in the past. The most commonly used sequential logic function is the flip-flop. A flip-flop's output data (Q) state changes only when there is a positive transition of its input clock (C) signal. At the time of this transition, the output data (Q) state changes to the state of its input data (D) signal. After the clock signal transition, the output data (Q) state maintains its state regardless of the state of the input data (D) signal. Each clock transition is referred to as a data cycle. Normally these data cycles occur at regularly scheduled intervals which represent the effective data rate of a circuit. Normal operation of the circuit will typically involve millions of data cycles.
To add testability to a circuit, flip-flops can be modified to facilitate the setting and reading of their data states using a data path that is independent of the data paths through combinational logic. This is referred to as Design For Test (DFT). FIG. 1 depicts a circuit 100 comprising four flip-flops 102, 104, 106, 108, with the combinational logic 110 of the circuit 100 enclosed in a “black box” for simplicity. FIG. 2 depicts a similar circuit 200 having a scan (or DFT structure) implemented therein. The scan chain is created by adding a signal multiplexer 202, 204, 206, 208 before the data input (D) of each flip-flop 102, 104, 106, 108. A single control signal called Scan Enable is added to control the selection of these multiplexers. When the Scan Enable signal is low, the circuit works as normal, meaning the data input to the flip-flops comes from the combinational logic 110 (e.g., data DO). When the Scan Enable signal is high, the input of each flip-flop 102, 104, 106, 108 is connected to the output of another flip-flop, or to an external pin (Scan Out) of the circuit 200. The data input to the first flip-flop 102 in the scan chain is also brought out to an external pin (Scan In) of the circuit 200. FIG. 3 depicts how this implementation facilitates the shifting in of a test pattern on the Scan In pin to every flip-flop 102, 104, 106, 108 in the circuit 200. After the test pattern is shifted in, the Scan Enable signal is brought low for one cycle, and the data outputs of the combinational logic 110 resulting from the shifted in test pattern are captured in the flip-flops 102, 104, 106, 108. The Scan Enable signal is then brought back high and the captured data results are shifted out of the Scan Out pin and compared against expected results by a test system. Any operational defect in the combinational logic 110 will cause one or more bits of the data output sequence to differ from the expected results.
Building upon the illustration of the principle discussed above, a typical device under test (e.g., an integrated circuit (IC)) might have thousands of flip-flops in each scan chain, and employ multiple scan chains. Also there are commonly several thousand different scan patterns applied in a test (a single pattern refers to the complete set of sequential data that is shifted into each flip-flop, requiring that each pattern contain one unique data state for each flip-flop in the design). This results in an extremely large volume of test data that is applied to and tested for during the testing of a complex device. Moreover the multiple scan chains within a device will rarely if ever have exactly identical length, so a test pattern will frequently have “don't care” states.
The role of DFT testing (or structural testing) may be to verify that a device is free of any manufacturing defects. During the execution of a test pattern, if a data state is detected that is different than the expected data state, it may be economical to terminate the test and categorize the IC as defective. However it may also be desirable to capture all failing data states in all patterns for the purpose of subsequently diagnosing the failures and determining which combinational logic element caused the fault. This diagnosis is normally done by a separate software program that analyzes the results captured by a test system (e.g., captured by automatic test equipment (ATE)). Thus, the automatic test equipment must be able to record the information required to perform this post analysis process.
FIG. 4 illustrates a device 400 having multiple scan chains, and FIG. 5 depicts an exemplary test system 500 for executing structural tests (also known as scan tests or DFT tests) of the device 400. A Data Pattern Memory is loaded with the test patterns to be applied to the device 400 and the data patterns expected to be read from the device. The test system 400 may have a selectable mode, for either 1) terminating the test whenever an error occurs (e.g., when an output data state differs from an expected data state), or 2) completing the entire pattern set and recording all of the errors that are observed. To accomplish this, a test system needs to have a Data Capture Memory. This memory may record the data cycle count and output pin for which an error is observed. Another mode of the Data Capture Memory is to record the raw (actual) states read from the scan outputs of the device 400.
A single fault in the combinational logic 110 may lead to several thousand errors that potentially need to be recorded in the Data Capture Memory. As an example, consider an IC design that has 20,000 flip-flops in each scan chain, and a test system that applies 10,000 scan patterns. In such a scenario, a single combinational logic fault might cause 10 flip-flops to fail in 25% of the patterns. This would result in 25,000 failures being recorded in the Data Capture Memory. While non-trivial, this data can be managed to a reasonable degree and “datalogged” to a file for post-processing to determine the location of the combinational logic fault.
However, a fault that exists in a scan chain path itself creates a significantly different diagnosis problem. FIG. 6 depicts the circuit 200 with a single “short” at the scan input to the multiplexer 204 preceding flip-flop 104. This defect will cause all scan data downstream of the “stuck-at” fault to have a logic “0” state. That is, logic “0”s will fill the flip-flops 104, 106 and 108 as the clock signal is toggled. The stuck-at defect therefore has two repercussions: 1) the test pattern applied to the combinational logic will be invalid, and 2) upon scanning a captured test pattern out of the Scan Out pin, the stuck-at defect (or blockage) creates an inability to observe any data captured in flip-flop 102. The result is a tremendous number of fails.
It is noted that, in the following description, like reference numbers appearing in different drawing figures refer to like elements/features. Often, therefore, like elements/features that appear in different drawing figures will not be described in detail with respect to each of the drawing figures.